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publication number s25FL128P_00 revision 04 issue date july 2, 2007 s25FL128P s25FL128P cover sheet 128 megabit cmos 3.0 volt flash memory with 104-mhz spi (serial pe ripheral interface) bus data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have be en in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinatio ns offered may occur.
2 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begun. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number s25FL128P_00 revision 04 issue date july 2, 2007 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 v read and program operations ? memory architecture ? 128mb uniform 256 kb sector product ? 128mb uniform 64 kb sector product ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? faster program time in accelerated programming mode (8.5 v?9.5 v on #wp/acc) in 1.2 ms (typical) ? erase ? 2 s typical 256 kb sector erase time ? 0.5 s typical 64 kb sector erase time ? 128 s typical bulk erase time ? sector erase (se) command (d8h) for 256 kb sectors; (20h or d8h) for 64kb sectors ? bulk erase command (c7h) for 256 kb sectors; (60h or c7h) for 64kb sectors ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? rdid (9fh), read_id (90h) and res (abh) commands to read manufacturer and device id information ? res command one-byte electronic signature for backward compatibility ? process technology ? manufactured on 0.09 m mirrorbit ? process technology ? package option ? industry standard pinouts ? 16-pin so package (300 mils) ? 8-contact wson package (6 x 8 mm) performance characteristics ? speed ? 104 mhz clock rate (maximum) ? power saving standby mode ? standby mode 200 a (max) ? deep power down mode 3 a (typical) memory protection features ? memory protection ? wp#/acc pin works in conjunction with status register bits to protect specified memory areas ? 256 kb uniform sector product: status register block protection bits (bp2, bp1, bp0) in status register configure parts of memory as read-only. ? 64kb uniform sector product: status register block protection bits (bp3, bp2, bp1, bp0) in status register configure parts of memory as read-only software features ? spi bus compatible serial interface hardware features ? x8 parallel programming mode (for 16-pin so package only) general description the s25FL128P is a 3.0 volt (2.7 v to 3.6 v), single- power-supply flash memory device. the device consists of 64 sectors of 256 kb memory, or 256 sectors of 64 kb memory. the device accepts data written to si (serial input) and outputs data on so (seria l output). the devices are designed to be programmed in-system wi th the standard system 3.0 volt v cc supply. the memory can be programmed 1 to 256 bytes at a time, using the page program command. the device supports sector erase and bulk erase commands. each device requires only a 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally generated and regulated voltages are provided for the program operations. this device requires a high voltage supply to wp#/acc pin for the accelerated programming mode. s25FL128P 128 megabit cmos 3.0 volt flash memory with 104-mhz spi (serial pe ripheral interface) bus data sheet (preliminary)
4 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. spansion spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 byte or page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 sector erase / bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3 monitoring write operations using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 data protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.7 hold mode (hold#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9. parallel mode (for 16-pin so package only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10. accelerated programming operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.1 read data bytes (read: 03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.2 read data bytes at higher speed (fast_read: 0bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.3 read identification (rdid: 9fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.4 read manufacturer and device id (read_id: 90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.5 write enable (wren: 06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.6 write disable (wrdi: 04h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.7 read status register (rdsr: 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.8 write status register (wrsr: 01h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 11.9 page program (pp: 02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.10 sector erase (se: 20h, d8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.11 bulk erase (be: c7h, 60h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.12 deep power down (dp: b9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.13 release from deep power down (res: abh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.14 release from deep power down and read electronic signature (res: abh) . . . . . . . . . . . 36 11.15 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12. program acceleration via wp#/acc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13. power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14. initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 16. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 19. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 20.1 so3 016 wide?16-pin plastic small outline package (300-mil body width) . . . . . . . . . . . . 45 20.2 wson 8-contact (6 x 8 mm) no-lead package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 21. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
july 2, 2007 s25FL128P_00_04 s25FL128P 5 data sheet (preliminary) figures figure 2.1 16-pin plastic small outline package (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.2 8-pin wson package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6.1 bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6.2 spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7.1 hold mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11.1 read data bytes (read) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11.2 parallel read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11.3 read data bytes at higher speed (fast_read) command sequence . . . . . . . . . . . . . . . 21 figure 11.4 read identification command sequence and data out sequence. . . . . . . . . . . . . . . . . . . . 22 figure 11.5 parallel read_id command sequence and data ou t sequence . . . . . . . . . . . . . . . . . . . . . 23 figure 11.6 serial read_id instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11.7 parallel read_id instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11.8 write enable (wren) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11.9 write disable (wrdi) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11.10 read status register (rdsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11.11 parallel read status register (rdsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . .28 figure 11.12 write status register (wrsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11.13 parallel write stat us register (wrsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11.14 page program (pp) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11.15 parallel page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11.16 sector erase (se) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11.17 bulk erase (be) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11.18 deep power down (dp) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11.19 release from deep power down (res) command se quence . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11.20 serial release from deep power down and read electronic signature (res) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 11.21 parallel release from deep power down and read electronic signature (res) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 12.1 acc program acceleration timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 13.1 power-up timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18.1 ac measurements i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19.1 spi mode 0 (0,0) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19.2 spi mode 0 (0,0) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19.3 hold# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 19.4 write protect setup and hold timing during wr sr when srwd=1 . . . . . . . . . . . . . . . . . . 44
6 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) tables table 5.1 s25FL128P valid combinations table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7.1 s25FL128P protected area sizes (uniform 256 kb sector) . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7.2 s25FL128P protected area sizes (uniform 64 kb sector) . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8.1 s25FL128P device organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 8.2 s25FL128P sector address table (uniform 256 kb se ctor) . . . . . . . . . . . . . . . . . . . . . . . . .15 table 8.3 s25FL128P sector address table (uniform 64 kb secto r) . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 11.1 manufacturer & device identification, rdid (9fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 11.2 read_id command and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 11.3 s25FL128P status register (uniform 256 kb sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 11.4 s25FL128P status register (uniform 64 kb sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 11.5 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 11.6 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 12.1 acc program acceleration specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 13.1 power-up timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 15.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 16.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 17.1 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 18.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 19.1 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
july 2, 2007 s25FL128P_00_04 s25FL128P 7 data sheet (preliminary) 1. block diagram s ram p s lo g ic array - l array - r rd data path io x d e c c s # s ck s i s o/po[7-0] gnd hold# wp#/acc v cc
8 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) figure 2.2 8-pin wson package (6 x 8 mm) 1 2 3 4 16 15 14 13 hold# vcc nc po2 po5 po6 si sck 5 6 7 8 12 11 10 9 wp#/acc gnd po3 po4 po1 po0 cs# so/po7 1 2 3 4 5 6 7 8 cs# vcc so hold# sck si gnd wson wp#/acc
july 2, 2007 s25FL128P_00_04 s25FL128P 9 data sheet (preliminary) 3. input/output descriptions 4. logic symbol signal name i/o description so (signal data output) output transfers data serially out of the device on the falling edge of sck. po[7?0] (parallel data input/output) input/output transfers parallel data into the device on the rising edge of sck or out of the device on the falling edge of sck. si (serial data input) input transfers data serially into the device. device latches commands, addresses, and program data on si on the rising edge of sck. sck (serial clock) input provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs# (chip select) input places device in active power mode when driven low. deselects device and places so at high impedance when high. after power-up, device requires a falling edge on cs# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold# (hold) input pauses any serial communication with the device without deselecting it. when driven low, so is at high impedance, and all input at si and sck are ignored. requires that cs# also be driven low. wp#/acc (write protect/accelerated programming) input when driven low, prevents any program or erase command from altering the data in the protected memory area specified by status register bits (bp bits). if the system asserts v hh on this pin, accelerated programming operation is provided. v cc input supply voltage gnd input ground c s # s o wp#/acc gnd s i s ck hold# v cc po[7-0] (for 16-pin s o p a ck a ge)
10 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 5. ordering information the ordering part number is formed by a valid combination of the following: table 5.1 s25FL128P valid combinations table note package marking omits leading ?s25? and speed, package, and model number form. 5.1 valid combinations table 5.1 lists the valid combinations configurations planned to be supported in volume for this device. s25fl 128 p 0x m f i 00 1 packing type 1 = tube 3 = 13? tape and reel model number (additional ordering options) 00 = uniform 64 kb sector product 01 = uniform 256 kb sector product temperature range i = industrial (?40c to + 85c) package materials f = lead (pb)-free package type m = 16-pin so package n = 8-pin wson package speed 0x = 104 mhz device technology p = 0.09 m mirrorbit ? process technology density 128 = 128 mbit device family s25fl spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory s25FL128P valid combinations package marking (see note) base ordering part number speed option package & temperature model number packing type s25FL128P 0x mfi, nfi 00 1, 3 FL128P + i + f 01 FL128P + i + fl
july 2, 2007 s25FL128P_00_04 s25FL128P 11 data sheet (preliminary) 6. spansion spi modes a microcontroller can use either of its two spi mo des to control spansion spi flash memory devices: ? cpol = 0, cpha = 0 (mode 0) ? cpol = 1, cpha = 1 (mode 3) input data is latched in on the rising edge of sck, and output data is available from the falling edge of sck for both modes. when the bus master is in standby mode, sck is as shown in figure 6.2 for each of the two modes: ? sck remains at 0 for (cpol = 0, cpha = 0 mode 0) ? sck remains at 1 for (cpol = 1, cpha = 1 mode 3) figure 6.1 bus master and memory devices on the spi bus note the write protect/accelerated programming (wp#/acc) and hold (hold#) signals should be driven high (logic level 1) or low (logi c level 0) as appropriate. figure 6.2 spi modes supported s pi interf a ce with (cpol, cpha) = (0, 0) or (1, 1) b us m as ter c s3 c s 2c s 1 s pi memory device s pi memory device s pi memory device c s # hold# c s # hold# c s # wp#/acc wp#/acc wp#/acc hold# s ck s o s i s ck s o s i s ck s o s i s o s i s ck m s b m s b s ck s ck s i s o cpha cpol 00 11 c s # mode 0 mode 3
12 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 7. device operations all spansion spi devices (s25fl-p) accept an d output data in bytes (8 bits at a time). 7.1 byte or page programming programming data requires two commands: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus da ta. the page program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. programming means that bits can either be left at 0, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. before this can be applied, the bytes of the memory need to be first erased to all 1?s (ffh) before any programming. 7.2 sector erase / bulk erase the sector erase (se) and bulk erase (be) commands set all the bits in a sector or the entire memory array to 1. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (se) or array-wide (be) level. before th is can be applied, the memory array need to be first erased to all 1's (ffh) before any programming. 7.3 monitoring write operations using the status register the host system can determine when a write status regist er, program, or erase o peration is complete by monitoring the write in progress (wip) bit in the stat us register. the read from status register command provides the state of the wip bit. 7.4 active power and standby power modes the device is enabled and in the active power mode when chip select (cs#) is low. when cs# is high, the device is disabled, but may still be in the active po wer mode until all program, erase, and write status register operations have completed. the device then goes into the standby power mode, and power consumption drops to i sb . the deep power down (dp) command provides additional data protection against inadvertent signals. after writing the dp command, the device ignores any further program or erase commands, and reduces its power consumption to i dp . 7.5 status register the status register contains the stat us and control bits that can be read or set by specific commands (see table table 11.6, command definitions on page 38 ): ? write in progress (wip): indicates whether the device is performi ng a write status register, program or erase operation. ? write enable latch (wel): indicates the status of the internal write enable latch. ? block protect (bp2, bp1, bp0 for uniform 256 kb sector product: bp 3, bp2, bp1, bp0 for uniform 64 kb sector product): non-volatile bits that define memory area to be software-protected against program and erase commands. ? status register write disable (srwd): places the device in the hardwa re protected mode when this bit is set to 1 and the wp#/acc input is driven low. in this mode, the non-volatile bits of the status register (srwd, bp3, bp2, bp1, bp0) become read-only bits. 7.6 data protection modes spansion spi flash memory devices provi de the following data protection methods: ? the write enable (wren) command: must be written prior to any command that modifies data. the wren command sets the write enable latch (wel ) bit. the wel bit resets (disables writes) on power-up or after the device completes the following commands : ? page program (pp)
july 2, 2007 s25FL128P_00_04 s25FL128P 13 data sheet (preliminary) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write status register (wrsr) ? software protected mode (spm): the block protect (bp2, bp1, bp0 for uniform 256 kb sector product: bp3, bp2, bp1, bp0 for uniform 64 kb sector product) bits define the section of th e memory array that can be read but not programmed or erased. table 7.1 shows the sizes and address ranges of protected areas that are defined by status register bits bp2:bp0 for uniform 256 kb sector product, bp3:bp0 for uniform 64 kb sector product). ? hardware protected mode (hpm): the write protect (wp#/acc) input and the status register write disable (srwd) bit together provide write protection. ? clock pulse count: the device verifies that all program, er ase, and write status register commands consist of a clock pulse count that is a multiple of eight before executing them. table 7.1 s25FL128P protected area sizes (uniform 256 kb sector) status register block protect bits memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0 0 0 none (0) 000000h-ffffffh (64) sa63:sa0 0 0 0 1 fc0000h-ffffffh (1) sa63 000000h-fbffffh (32) sa62:sa0 1/64 0 1 0 f80000h-ffffffh (2) sa63:sa62 000000h-f7ffffh (16) sa61:sa0 1/32 0 1 1 f00000h-ffffffh (4) sa63:sa60 000000h-efffffh (8) sa59:sa0 1/16 1 0 0 e00000h-ffffffh (8) sa63:sa56 000000h-dfffffh (4) sa55:sa0 1/8 1 0 1 c00000h-ffffffh (16) sa63:sa48 000000h-bfffffh (2) sa47:sa0 1/4 1 1 0 800000h-ffffffh (32) sa63:sa32 000000h-7fffffh (1) sa31:sa0 1/2 1 1 1 000000h-ffffffh (64) sa63:sa0 none (0) all table 7.2 s25FL128P protected area sizes (uniform 64 kb sector) status register block protect bits memory array protected portion of total memory area bp3 bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0000 none (0) 00 0000h-ffffffh (256) sa255:sa0 0 0001fe0 000h-ffffffh (2) sa255:sa254 000000h-fdffffh (128) sa253:sa0 1/128 0010fc00 00h-ffffffh (4) sa255:sa252 000000h-fbffffh (64) sa251:sa0 1/64 0011f 80000h-ffffffh (8) sa255:sa248 000000h-f7ffffh (32) sa247:sa0 1/32 0100f 00000h-ffffffh (16) sa255:sa240 000000h-efffffh (16) sa239:sa0 1/16 0101e0 0000h-ffffffh (32) sa255:sa224 000000h-dfffffh (8) sa223:sa0 1/8 0110c00 000h-ffffffh (64) sa255:sa192 000000h-bfffffh (4) sa191:sa0 1/4 0111 800000h-ffffffh (128) sa255:sa128 000000h-7fffffh (2) sa127:sa0 1/2 1000 000000h-ffffffh (256) sa255:sa0 none (0) all 1001 000000h-ffffffh (256) sa255:sa0 none (0) all 1010 000000h-ffffffh (256) sa255:sa0 none (0) all 1011 000000h-ffffffh (256) sa255:sa0 none (0) all 1100 000000h-ffffffh (256) sa255:sa0 none (0) all 1101 000000h-ffffffh (256) sa255:sa0 none (0) all 1110 000000h-ffffffh (256) sa255:sa0 none (0) all 1111 000000h-ffffffh (256) sa255:sa0 none (0) all
14 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 7.7 hold mode (hold#) the hold input (hold#) stops any serial communicatio n with the device, but does not terminate any write status register, program or erase operation that is currently in progress. the hold mode starts on the falling edge of hold# if sck is also low (see figure 7.1 on page 14 , standard use). if the falling edge of hold# does not occur while sc k is low, the hold mode begins after the next falling edge of sck (non-standard use). the hold mode ends on the rising edge of hold# signal (s tandard use) if sck is also low. if the rising edge of hold# does not occur while sck is low, the hold mode ends on the next falling edge of clk (non- standard use) see figure 7.1 . the so output is high impedance, and the si and sck in puts are ignored (don?t care) for the duration of the hold mode. cs# must remain low for the entire duration of the hold mode to ensure that the device internal logic remains unchanged. if cs# goes high while the device is in the ho ld mode, the internal logic is reset. to prevent the device from reverting to the hold mode when device communication is resumed, hold# must be held high, followed by driving cs# low. figure 7.1 hold mode operation 8. sector address table table 8.1 shows the size of the memory array, sectors, and pages. the device uses pages to cache the program data before the data is programmed into the memory array. each page or byte can be individually programmed (bits are changed from 1 to 0). the data is erased (bits are changed from 0 to 1) on a sector- or device-wide basis using the se or be commands. table 8.2 shows the starting and ending address for each sector. the complete set of sectors compri ses the memory array of the flash device. s ck hold# hold condition ( s t a nd a rd us e) hold condition (non- s t a nd a rd us e) table 8.1 s25FL128P device organization each device has each sector has each page has 16,777,216 262144 (256 kb sector) 65536 (64 kb sector) 256 bytes 65,536 1024 (256 kb sector) 256 (64 kb sector) ? pages 64 (256 kb sector) 256 (64 kb sector) ? ? sectors
july 2, 2007 s25FL128P_00_04 s25FL128P 15 data sheet (preliminary) table 8.2 s25FL128P sector address table (uniform 256 kb sector) sector address range sector address range 63 fc0000h ffffffh 31 7c0000h 7fffffh 62 f80000h fbffffh 30 780000h 7bffffh 61 f40000h f7ffffh 29 740000h 77ffffh 60 f00000h f3ffffh 28 700000h 73ffffh 59 ec0000h efffffh 27 6c0000h 6fffffh 58 e80000h ebffffh 26 680000h 6bffffh 57 e40000h e7ffffh 25 640000h 67ffffh 56 e00000h e3ffffh 24 600000h 63ffffh 55 dc0000h dfffffh 23 5c0000h 5fffffh 54 d80000h dbffffh 22 580000h 5bffffh 53 d40000h d7ffffh 21 540000h 57ffffh 52 d00000h d3ffffh 20 500000h 53ffffh 51 cc0000h cfffffh 19 4c0000h 4fffffh 50 c80000h cbffffh 18 480000h 4bffffh 49 c40000h c7ffffh 17 440000h 47ffffh 48 c00000h c3ffffh 16 400000h 43ffffh 47 bc0000h bfffffh 15 3c0000h 3fffffh 46 b80000h bbffffh 14 380000h 3bffffh 45 b40000h b7ffffh 13 340000h 37ffffh 44 b00000h b3ffffh 12 300000h 33ffffh 43 ac0000h afffffh 11 2c0000h 2fffffh 42 a80000h abffffh 10 280000h 2bffffh 41 a40000h a7ffffh 9 240000h 27ffffh 40 a00000h a3ffffh 8 200000h 23ffffh 39 9c0000h 9fffffh 7 1c0000h 1fffffh 38 980000h 9bffffh 6 180000h 1bffffh 37 940000h 97ffffh 5 140000h 17ffffh 36 900000h 93ffffh 4 100000h 13ffffh 35 8c0000h 8fffffh 3 0c0000h 0fffffh 34 880000h 8bffffh 2 080000h 0bffffh 33 840000h 87ffffh 1 040000h 07ffffh 32 800000h 83ffffh 0 000000h 03ffffh
16 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) table 8.3 s25FL128P sector address table (uniform 64 kb sector) (sheet 1 of 2) sector address range sector address range sector address range 255 ff0000h ffffffh 207 cf0000h cfffffh 159 9f0000h 9fffffh 254 fe0000h feffffh 206 ce0000h ceffffh 158 9e0000h 9effffh 253 fd0000h fdffffh 205 cd0000h cdffffh 157 9d0000h 9dffffh 252 fc0000h fcffffh 204 cc0000h ccffffh 156 9c0000h 9cffffh 251 fb0000h fbffffh 203 cb0000h cbffffh 155 9b0000h 9bffffh 250 fa0000h faffffh 202 ca0000h caffffh 154 9a0000h 9affffh 249 f90000h f9ffffh 201 c90000h c9ffffh 153 990000h 99ffffh 248 f80000h f8ffffh 200 c80000h c8ffffh 152 980000h 98ffffh 247 f70000h f7ffffh 199 c70000h c7ffffh 151 970000h 97ffffh 246 f60000h f6ffffh 198 c60000h c6ffffh 150 960000h 96ffffh 245 f50000h f5ffffh 197 c50000h c5ffffh 149 950000h 95ffffh 244 f40000h f4ffffh 196 c40000h c4ffffh 148 940000h 94ffffh 243 f30000h f3ffffh 195 c30000h c3ffffh 147 930000h 93ffffh 242 f20000h f2ffffh 194 c20000h c2ffffh 146 920000h 92ffffh 241 f10000h f1ffffh 193 c10000h c1ffffh 145 910000h 91ffffh 240 f00000h f0ffffh 192 c00000h c0ffffh 144 900000h 90ffffh 239 ef0000h efffffh 191 bf0000h bfffffh 143 8f0000h 8fffffh 238 ee0000h eeffffh 190 be0000h beffffh 142 8e0000h 8effffh 237 ed0000h edffffh 189 bd0000h bdffffh 141 8d0000h 8dffffh 236 ec0000h ecffffh 188 bc0000h bcffffh 140 8c0000h 8cffffh 235 eb0000h ebffffh 187 bb0000h bbffffh 139 8b0000h 8bffffh 234 ea0000h eaffffh 186 ba0000h baffffh 138 8a0000h 8affffh 233 e90000h e9ffffh 185 b90000h b9ffffh 137 890000h 89ffffh 232 e80000h e8ffffh 184 b80000h b8ffffh 136 880000h 88ffffh 231 e70000h e7ffffh 183 b70000h b7ffffh 135 870000h 87ffffh 230 e60000h e6ffffh 182 b60000h b6ffffh 134 860000h 86ffffh 229 e50000h e5ffffh 181 b50000h b5ffffh 133 850000h 85ffffh 228 e40000h e4ffffh 180 b40000h b4ffffh 132 840000h 84ffffh 227 e30000h e3ffffh 179 b30000h b3ffffh 131 830000h 83ffffh 226 e20000h e2ffffh 178 b20000h b2ffffh 130 820000h 82ffffh 225 e10000h e1ffffh 177 b10000h b1ffffh 129 810000h 81ffffh 224 e00000h e0ffffh 176 b00000h b0ffffh 128 800000h 80ffffh 223 df0000h dfffffh 175 af0000h afffffh 127 7f0000h 7fffffh 222 de0000h deffffh 174 ae0000h aeffffh 126 7e0000h 7effffh 221 dd0000h ddffffh 173 ad0000h adffffh 125 7d0000h 7dffffh 220 dc0000h dcffffh 172 ac0000h acffffh 124 7c0000h 7cffffh 219 db0000h dbffffh 171 ab0000h abffffh 123 7b0000h 7bffffh 218 da0000h daffffh 170 aa0000h aaffffh 122 7a0000h 7affffh 217 d90000h d9ffffh 169 a90000h a9ffffh 121 790000h 79ffffh 216 d80000h d8ffffh 168 a80000h a8ffffh 120 780000h 78ffffh 215 d70000h d7ffffh 167 a70000h a7ffffh 119 770000h 77ffffh 214 d60000h d6ffffh 166 a60000h a6ffffh 118 760000h 76ffffh 213 d50000h d5ffffh 165 a50000h a5ffffh 117 750000h 75ffffh 212 d40000h d4ffffh 164 a40000h a4ffffh 116 740000h 74ffffh 211 d30000h d3ffffh 163 a30000h a3ffffh 115 730000h 73ffffh 210 d20000h d2ffffh 162 a20000h a2ffffh 114 720000h 72ffffh 209 d10000h d1ffffh 161 a10000h a1ffffh 113 710000h 71ffffh 208 d00000h d0ffffh 160 a00000h a0ffffh 112 700000h 70ffffh
july 2, 2007 s25FL128P_00_04 s25FL128P 17 data sheet (preliminary) 111 6f0000h 6fffffh 71 470000h 47ffffh 31 1f0000h 1fffffh 110 6e0000h 6effffh 70 460000h 46ffffh 30 1e0000h 1effffh 109 6d0000h 6dffffh 69 450000h 45ffffh 29 1d0000h 1dffffh 108 6c0000h 6cffffh 68 440000h 44ffffh 28 1c0000h 1cffffh 107 6b0000h 6bffffh 67 430000h 43ffffh 27 1b0000h 1bffffh 106 6a0000h 6affffh 66 420000h 42ffffh 26 1a0000h 1affffh 105 690000h 69ffffh 65 410000h 41ffffh 25 190000h 19ffffh 104 680000h 68ffffh 64 400000h 40ffffh 24 180000h 18ffffh 103 670000h 67ffffh 63 3f0000h 3fffffh 23 170000h 17ffffh 102 660000h 66ffffh 62 3e0000h 3effffh 22 160000h 16ffffh 101 650000h 65ffffh 61 3d0000h 3dffffh 21 150000h 15ffffh 100 640000h 64ffffh 60 3c0000h 3cffffh 20 140000h 14ffffh 99 630000h 63ffffh 59 3b0000h 3bffffh 19 130000h 13ffffh 98 620000h 62ffffh 58 3a0000h 3affffh 18 120000h 12ffffh 97 610000h 61ffffh 57 390000h 39ffffh 17 110000h 11ffffh 96 600000h 60ffffh 56 380000h 38ffffh 16 100000h 10ffffh 95 5f0000h 5fffffh 55 370000h 37ffffh 15 0f0000h 0fffffh 94 5e0000h 5effffh 54 360000h 36ffffh 14 0e0000h 0effffh 93 5d0000h 5dffffh 53 350000h 35ffffh 13 0d0000h 0dffffh 92 5c0000h 5cffffh 52 340000h 34ffffh 12 0c0000h 0cffffh 91 5b0000h 5bffffh 51 330000h 33ffffh 11 0b0000h 0bffffh 90 5a0000h 5affffh 50 320000h 32ffffh 10 0a0000h 0affffh 89 590000h 59ffffh 49 310000h 31ffffh 9 090000h 09ffffh 88 580000h 58ffffh 48 300000h 30ffffh 8 080000h 08ffffh 87 570000h 57ffffh 47 2f0000h 2fffffh 7 070000h 07ffffh 86 560000h 56ffffh 46 2e0000h 2effffh 6 060000h 06ffffh 85 550000h 55ffffh 45 2d0000h 2dffffh 5 050000h 05ffffh 84 540000h 54ffffh 44 2c0000h 2cffffh 4 040000h 04ffffh 83 530000h 53ffffh 43 2b0000h 2bffffh 3 030000h 03ffffh 82 520000h 52ffffh 42 2a0000h 2affffh 2 020000h 02ffffh 81 510000h 51ffffh 41 290000h 29ffffh 1 010000h 01ffffh 80 500000h 50ffffh 40 280000h 28ffffh 0 000000h 00ffffh 79 4f0000h 4fffffh 39 270000h 27ffffh 78 4e0000h 4effffh 38 260000h 26ffffh 77 4d0000h 4dffffh 37 250000h 25ffffh 76 4c0000h 4cffffh 36 240000h 24ffffh 75 4b0000h 4bffffh 35 230000h 23ffffh 74 4a0000h 4affffh 34 220000h 22ffffh 73 490000h 49ffffh 33 210000h 21ffffh 72 480000h 48ffffh 32 200000h 20ffffh table 8.3 s25FL128P sector address table (uniform 64 kb sector) (sheet 2 of 2) sector address range sector address range sector address range
18 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 9. parallel mode (for 16-pin so package only) the parallel mode provides 8 bits of input/output to increase factory pro duction throughput at the customer manufacturing facilities. this function is recommended fo r increasing production throughput. entering parallel mode requires issuing the enter parallel mode comm and (55h). after writing the parallel mode entry command and pulling cs# high, the available command s are read, write enable (wren), write disable (wrdi), page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), read status register (rdsr), release from deep power down/release from deep power down and read electronic signature (res), write e nable (wren), write disable (wrdi), deep power down (dp), read identification (rdid) and read id (read_id). the flash memory will remain in parallel mode until either the parallel mode exit command (45h) is issued, or until a power-down / power-up sequence has been complete d, after which the flash memory will exit parallel mode automatically and switch back to serial mode (no power-down will be necessary to switch back to serial mode if the parallel mode exit command is issued). in parallel mode, the maximum sck clock frequency is limited to 6 mhz for read data bytes and 10 mhz for other operations. po[6-0] can be left unconnected if the parallel mode functions are not needed. fast-read command is not applicable in parallel mode. 10. accelerated programming operation the device offers accelerated program operations thr ough the acc function. this function is primarily intended to allow faster manufacturing through put at the factory. if the system asserts v hh on this pin, the device uses the higher voltage on the pin to reduce th e time required for program operations. removing v hh from the wp#/acc pin returns the device to normal ope ration. note that the wp #/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, the wp#/ acc pin must not be left floating or unconnected; inconsistent behavior of the device may result.
july 2, 2007 s25FL128P_00_04 s25FL128P 19 data sheet (preliminary) 11. command definitions the host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. on the first rising edge of sck a fter cs# is driven low, the device accepts the one-byte command on si (all commands are one byte long), most significant bit first. each successive bit is latched on the rising edge of sck. table 11.6 on page 38 lists the complete set of commands. every command sequence begins with a one-byte comm and code. the command may be followed by address, data, both, or nothing, depending on the comma nd. cs# must be driven high after the last bit of the command sequence has been written. the read data bytes (read), read status regi ster (rdsr), read data bytes at higher speed (fast_read) and read identification (rdid) command sequences are followed by a data output sequence on so. cs# can be driven high after any bit of th e sequence is output to terminate the operation. the page program (pp), sector erase (se), bulk eras e (be), write status regi ster (wrsr), write enable (wren), or write disable (wrdi) commands require that cs# be driven high at a byte boundary, otherwise the command is not executed. since a byte is composed of eight bits, cs# must therefore be driven high when the number of clock pulses after cs# is driven low is an exact multiple of eight. the device ignores any attempt to access the memory array during a write status register, program, or erase operation, and continue s the operation uninterrupted. 11.1 read data bytes (read: 03h) 11.1.1 serial mode the read data bytes (read-serial mode) command reads data from the memory array at the frequency (f sck ) presented at the sck input, with a maximum speed of 40 mhz. the host system must first select the device by driving cs# low. the read command is then written to si, followed by a 3-byte address (a23-a0). each bit is latched on the rising edge of sck. the memory array data, at that address, are output serially on so at a frequency f sck , on the falling edge of sck. figure 11.1 and table 11.6 detail the read command sequence. th e first byte specified can be at any location. the device automatically in crements to the next higher address afte r each byte of data is output. the entire memory array can therefore be read with a single read command. when the highest address is reached, the address counter reverts to 00000h, al lowing the read sequence to continue indefinitely. the read command is terminated by driving cs# high at any time during data output. the device rejects any read command issued while it is executing a progr am, erase, or write status register operation, and continues the operation uninterrupted. figure 11.1 read data bytes (read) command sequence comm a nd 24-bit addre ss hi-z m s b m s b d a t a o u t 1 d a t a o u t 2 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 3 0 29 2 8 10 9 8 7 6 5 4 3 2 1 7 6 5 2 3 22 21 4 3 2 1 0 3 2 10 7 s o s i s ck c s # mode 3 mode 0
20 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.1.2 parallel mode in parallel mode, the maximum sck clock frequency is 6 mhz. the device requires a single clock cycle instead of eight clock cycles to access the next data byte. the memory a rray output will be the same as in the serial mode. the only difference is th at a byte of data is output per clo ck cycle instead of a single bit. this means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles instead of in 2,048 clock cycles. figure 11.2 parallel read instruction sequence notes 1. 1st byte = ?03h?. 2. 2nd byte = address 1, msb first (bits 23 through 16). 3. 3rd byte = address 2, msb first (bits 15 through 8). 4. 4th byte = address 3, msb first (bits 7 through 0). 5. from the 5th byte, so will output the array data. 6. in parallel mode, the maximum clock frequency (fsck) is 6 mhz. 7. for parallel mode operation, the device requires an enter parallel mode command (55h) before the read command. an exit parall el mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode. c s # s ck s i po[7-0] high imped a nce d a t a o u t in s tr u ction 24-bit addre ss
july 2, 2007 s25FL128P_00_04 s25FL128P 21 data sheet (preliminary) 11.2 read data bytes at higher speed (fast_read: 0bh) the fast_read command reads data from the memory array at the frequency (f sck ) presented at the sck input, with a maximum speed of 104 mh z. the host system must first select the device by driving cs# low. the fast_read command is then written to si, follow ed by a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. the memory array data, at that address, are output serially on so at a frequency f sck , on the falling edge of sck. the fast_read command sequence is shown in figure 11.3 and table 11.6 . the first byte specified can be at any location. the device automat ically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single fast_read command. when the highest address is reached, the ad dress counter reverts to 00000h, allowing the read sequence to continue indefinitely. the fast_read command is terminated by driving cs# high at any time during data output. the device rejects any fast_read command issued while it is ex ecuting a program, erase, or write status register operation, and continues the operation uninterrupted. no te that the fast_read command is not valid in parallel mode. figure 11.3 read data bytes at higher speed (fast_read) command sequence c s # s ck s i s o comm a nd 24-bit addre ss d u mmy byte hi-z data out 1 data out 2 m s b m s b 01 2 3 4 56 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 2 3 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7 mode 3 mode 0
22 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.3 read identification (rdid: 9fh) 11.3.1 serial mode the read identification (rdid) instru ction opcode allows the 8-bit manufa cturer identification to be read, follow by two bytes of device identification. the manufa cturer identification is assi gned by jedec. the device identification is assigned by the device manufacturer. any read identification (rdid) instruction opcode issued while a program, erase, or write cycle is in progress is not decoded and has no effect on execution of the program, erase, or write cycle that is in progress. the device is first selected by driving the cs# chip select input pin to the logic low state. after this, the rdid 8-bit instruction opcode is shifted in onto the si serial input pin. after the last bit of the rdid instruction opcode is shifted into the device, a by te of manufacturer identification, tw o bytes of device identification and two bytes of extended device identificat ion will be shifted sequentially out of the so serial output pin. each bit is shifted out during the falling edge of the sck serial clock signal. the maximum clock frequency for the rdid (9fh) command is at 40mhz (normal read). the read identification (rdid) instru ction sequence is terminat ed by driving the cs# chip select input pin to the logic high state anytime during data output. after issuing any read id instruction opcodes (90h, 9fh, abh), driving the cs# chip select input pin to the l ogic high state will automatically send the device into the standby mode. driving the cs# chip select input pin to the logic low state again will automatically send the device out of the standby mode and into the active mode. figure 11.4 read identification command sequence and data out sequence c s # s ck s i s o high imped a nce m a n u f a ct u rer / device identific a tion extended device identific a tion m s b m s b in s tr u ction 012 3 4567 8 910 2 8 2 3 22 21 15 14 1 3 3 210 3 210 29 3 0 3 1 3 2 33 3 444454647
july 2, 2007 s25FL128P_00_04 s25FL128P 23 data sheet (preliminary) 11.3.2 parallel mode in parallel mode, the maximum sck clock frequency is 10 mhz. the device requires a single clock cycle instead of eight clock cycles to acce ss the next data byte. th e method of memory c ontent output will be the same compared to the serial mode. the only difference is that a byte of data is out put per clock cycle instead of a single bit. in this case, th e manufacturer identi fication will be output during the first byte cycle and the device identification during the second and third byte cycles out of the po7-po 0 serial output pi ns. to read id in parallel mode requires a parallel mode entry comm and (55h) to be issued before the rdid command. once in the parallel mode, the flash memory will not exit parallel mode until a parallel mode exit (45h) command is given to the flash device, or upon power down/power up sequence. figure 11.5 parallel read_id command sequence and data out sequence table 11.1 manufacturer & device identification, rdid (9fh) device manufacturer identification device identification extended device identification byte 0 byte 1 byte 2 byte 3 byte 4 uniform 256 kb sector 01h 20h 18h 03h 00h uniform 64 kb sector 01h 20h 18h 03h 01h c s # s ck s i po[7-0] high imped a nce in s tr u ction m a n u f a ct u rer/device identific a tion 012 3 4567 8 9101112 byte 0 byte 1 byte 2 byte 3 byte 4
24 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.4 read manufacturer and device id (read_id: 90h) 11.4.1 serial mode the read_id (90h) instruction identifies the device m anufacturer id and the device id. the instruction is initiated by driving the cs# pin low and shifting in (via the si input pin) the instruction code ?90h? followed by a 24-bit address of xxxxx0h. (x: high or low) followin g this, the manufacturer id and the device id are shifted out on so output pin starting after the falling edge of the sck serial clock input signal. the manufacturer id and the device id are always shifted out on the so output pin with the msb first, as shown in figure 11.6 . if the 24-bit address is set to xxxxx1h, then the device id is read out first followed by the manufacturer id. note that the upper 23 bits of the address do not have to be 0?s and can be don?t cares. once the device is in read_id mode, the manufactu rer id and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on the cs# input pin. after the first 24-bit address is provided, the user must wait 16 clock cycles for both th e manufacturer id and device id to be output on the so output pin. the maximum clo ck frequency for the read_id (90h) command is at 104mhz (fast read). parallel mode the maximum clock frequency is 10mhz. the manufacturer id & device id is output continuous ly until terminated by a low to high transition on cs# chip select input pin. after issuing read_id instruction, driving the cs# chip select input pin to the logic high state will automatically send the device into the standby mode. driving the cs# chip select input pin to the logic low state again will automatically sent the device out of the standby mode and into the active mode. figure 11.6 serial read_id instruction sequence c s # s ck s i s o high imped a nce 24-bit addre ss high imped a nce in s tr u ction 90h 012 3 4567 2 3 22 21 20 19 1 8 17 16 8 9 1011121 3 14 15 15 14 1 3 12 11 10 9 8 16 17 1 8 19 20 21 22 2 3 c s # s ck s i s o high imped a nce m a n u f a ct u rer id device id 24-bit addre ss m s b m s b 7654 3 210 7654 3 2107654 3 210 24 25 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 94041424 3 44 45 46 47
july 2, 2007 s25FL128P_00_04 s25FL128P 25 data sheet (preliminary) 11.4.2 parallel mode the maximum clock frequency allowed on the sck input pin in parallel mode is 10 mhz. the parallel mode entry command (55h) must be issued before writing th e read_id command. once in the parallel mode, the flash memory will not exit parallel mode until a parallel mode exit (45h) command is given to the flash device, or upon power-down/power-up sequence. figure 11.7 parallel read_id instruction sequence 11.5 write enable (wren: 06h) the write enable (wren) command (see figure 11.8 ) sets the write enable latch (wel) bit to a 1, which enables the device to accept a write status register , program, or erase command . the wel bit must be set prior to every page program (pp), erase (se or be) and write stat us register (wrsr) command. the host system must first drive cs# low, writ e the wren command, and then drive cs# high. figure 11.8 write enable (wren) command sequence table 11.2 read_id command and data description address data manufacturer identification 00000h 01h device identification (memory capacity) 00001h 17h 1 3 1 20 0 in s tr u ction 2 d u mmy byte s 15 1 3 14 1 3 20 high imped a nce m s b 90h m a n u f a ct u re id device id 7 2 8 29 20 3 1 3 2 3 add (1) byte 1 byte 2 1 3 20 7654 3 24 25 26 2 22 0 21 2 3 3 4 3 c s # s ck s i po[7-0] 4567 8 9 c s # s ck s i s o/po[7-0] hi-z comm a nd 01 2 3 45 67 mode 3 mode 0
26 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.6 write disable (wrdi: 04h) the write disable (wrdi) command (see figure 11.9 ) resets the write enable latch (wel) bit to a 0, which disables the device from accepting a write status register, program, or erase command. the host system must first drive cs# low, write the wr di command, and then drive cs# high. any of following conditions resets the wel bit: ? power-up ? write disable (wrdi) command completion ? write status register (wrsr) command completion ? page program (pp) command completion ? sector erase (se) command completion ? bulk erase (be) command completion figure 11.9 write disable (wrdi) command sequence 11.7 read status register (rdsr: 05h) 11.7.1 serial mode the read status register (rds r) command outputs the state of the status register bits. table 11.3 shows the status register bits and their functions. the rdsr command may be written at any time, even wh ile a program, erase, or write status register operation is in progress. the host system should check the write in progress (wip) bit before sending a new command to the device if an operation is already in progress. figure 11.10 shows the rdsr command sequence, which also shows that it is possible to read the status register continuously until cs# is driven high. 0 1 2 3 4 5 6 7 comm a nd c s # hi-z s ck s i s o/po[7-0] mode 3 mode 0 table 11.3 s25FL128P status register (uniform 256 kb sector) bit status register bit bit function description 7srwd status register write disable 1 = protects when wp#/acc is low 0 = no protection, even when wp#/acc is low 6 don?t care ? ? 5 0 ? not used 4bp2 block protect 000?111 = protects upper half of address range in 7 sizes. 3bp1 2bp0 1 wel write enable latch 1 = device accepts write status register, program, or erase commands 0 = ignores write status register, program, or erase commands 0 wip write in progress 1 = device busy. a write status register, program, or erase operation is in progress 0 = ready. device is in standby mode and can accept commands.
july 2, 2007 s25FL128P_00_04 s25FL128P 27 data sheet (preliminary) figure 11.10 read status register (rdsr) command sequence table 11.4 s25FL128P status register (uniform 64 kb sector) bit status register bit bit function description 7srwd status register write disable 1 = protects when wp#/acc is low 0 = no protection, even when wp#/acc is low 6 don?t care ? ? 5bp3 block protect 0000?1111= protects upper half of address range in 8 sizes. 4bp2 3bp1 2bp0 1 wel write enable latch 1 = device accepts write status register, program, or erase commands 0 = ignores write status register, program, or erase commands 0 wip write in progress 1 = device busy. a write status register, program, or erase operation is in progress 0 = ready. device is in standby mode and can accept commands. comm a nd hi-z m s b m s b s t a t us regi s ter o u t s t a t us regi s ter o u t 0 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 s o s i s ck c s # mode 3 mode 0
28 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.7.2 parallel mode when the device is in parallel mode, the maximum sck clock frequency is 10 mhz. the device requires a single clock cycle instead of eight clock cycles to acce ss the next data byte. the method of memory content output will be the same compared to outside of parallel mode. the only difference is that a byte of data is output per clock cycle instead of a si ngle bit. the status register cont ents can be read ou t on the po[7-0] serial output pins cont inuously by applying mu ltiples of clock cycles. figure 11.11 parallel read status register (rdsr) instruction sequence notes 1. instruction byte = 05h. 2. under parallel mode, the fastest access clock frequency (fsck) will be changed to a maximum of 10mhz (sck pin clock frequency ). 3. to read status register in parallel mode requires a parallel mode entry command (55h) to be issued before the rdsr command. o nce in the parallel mode, the flash memory will not exit the parallel mode until a parallel mode exit (45h) command is given to the flash device, or upon power down / power up sequence. 11.7.3 status regist er bit descriptions the following describes the status and control bits of the status register, and applies to both serial and parallel modes. write in progress (wip) bit: indicates whether the device is busy performing a write status register, program, or erase operation. this bit is read-only, and is controlled internally by the device. if wip is 1, one of these operations is in progress; if wip is 0, no such operation is in progress. write enable latch (wel) bit: determines whether the device will accept and execute a write status register, program, or erase command. when set to 1, the device accepts these commands; when set to 0, the device rejects the commands. this bit is set to 1 by writing the wren command, and set to 0 by the wrdi command, and is also automatically reset to 0 after the completion of a write status register, program, or erase operation. wel cannot be directly set by the wrsr command. block protect (bp2, bp1, bp0) bits for uniform 256kb sector product: (bp3, bp2, bp1, bp0) for uniform 64kb sector product: define the portion of the memory ar ea that will be protected against any changes to the stored data. the writ e status register (wrsr) command controls these bits, which are non- volatile. when one or more of these bits is set to 1, the corresponding memory area (see table 7.1 on page 13 ) is protected against page program (pp) and se ctor erase (se) command s. if the hardware protected mode is enabled, bp2:bp0 (or bp3:bp0) ca nnot be changed. the bulk erase (be) command is executed only if all block protect bits are 0. status register writ e disable (srwd) bit: provides data protection when used together with the write protect (wp#/acc) signal. when srwd is set to 1 and wp#/acc is driven low, the device enters the hardware protected mode. the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the device ignores any write status register (wrsr) command. comm a nd hi-z s t a t us regi s ter o u t 0 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 mode 3 mode 0 byte 1 byte 2 byte n s ck s i c s # po[7-0]
july 2, 2007 s25FL128P_00_04 s25FL128P 29 data sheet (preliminary) 11.8 write status register (wrsr: 01h) the write status register (wrsr) command changes the bits in the status register. a write enable (wren) command, which itself sets the write enable latch (wel) in the status register, is required prior to writing the wrsr command. table 11.3, s25FL128P status register (uniform 256 kb sector) on page 26 shows the status register bits and their functions. the host system must drive cs# low, write the wrsr command, and the appropriate data byte on si ( figure 11.12 ). the wrsr command cannot change the state of the write enable latch (bit 1). the wren command must be used for that purpose. bit 0 is a st atus bit controlled internally by the flash device. bits 6 and 5 are always read as 0 and have no user significance. the wrsr command also controls the value of the stat us register write disable (srwd) bit. the srwd bit and wp#/acc together place the device in the hardware protected mode (hpm). the device ignores all wrsr commands once it enters the hardware protected mode (hpm). table 11.5 shows that wp#/acc must be driven low and the srwd bit must be 1 for this to occur. figure 11.12 write status register (wrsr) command sequence figure 11.13 parallel write status regist er (wrsr) command sequence notes 1. instruction byte = 01h 2. in parallel mode, the maximum access clock frequency (fsck) is 10 mhz (sck pin clock frequency). 3. writing to the status register in parallel mode requires a parallel mode entry command (55h) to be issued before the rdsr com mand. once in the parallel mode, the flash memory will not exit the parallel mode until a parallel mode exit (45h) command is given t o the flash device, or upon power-down or power-up sequence. hi-z m s b comm a nd s t a t us regi s ter in c s # s ck s i s o 0 12 3 4 5 6 7 7654 3 210 8 9 10 11 12 1 3 14 15 mode 0 mode 3 hi-z comm a nd s t a t us regi s ter in c s # s ck s i po[7-0] 0 12 3 4 5 6 7 byte 1 8 9 10 11 12 1 3 14 15 mode 0 mode 3
30 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) note as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 7.1 on page 13 . table 11.5 shows that neither wp#/acc or srwd bit by themselves can enable hpm. the device can enter hpm either by setting the srwd bit after driving wp#/ acc low, or by driving wp#/acc low after setting the srwd bit. however, the device disables hpm only when wp#/acc is driven high. note that hpm only protects against changes to the status register. since bp2 :bp0 (or bp3:bp0) cannot be changed in hpm, the size of the protected area of the memory array cannot be changed. note that hpm provides no protection to the memory array area outs ide that specified by bloc k protect bits (software protected mode, or spm). if wp#/acc is permanently tied high , hpm can never be activated, and only the spm (block protect bits of the status register) can be used. 11.9 page program (pp: 02h) 11.9.1 serial mode the page program (pp) command changes specified bytes in the memory array (from 1 to 0 only). a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the pp command, three address bytes, and at least one data byte on si. cs# must be driven low for the enti re duration of the pp sequence. the command sequence is shown in figure 11.14 and table 11.6 . the device programs only the last 256 data bytes sent to the device. if the number of data bytes exceeds this limit, the bytes sent before the last 256 bytes are disca rded, and the device begins programming the last 256 bytes sent at the starting address of the specified page. this may result in data being programmed into different addresses within the same page than expected. if fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses. the host system must drive cs# high after the device has latc hed the 8th bit of the data byte, otherwise the device does not execute the pp comma nd. the pp operation begins as soon as cs# is driven high. the device internally controls the timing of th e operation, which requires a period of t pp . the status register may be read to check the value of the write in progress (w ip) bit while the pp operation is in progress. the wip bit is 1 during the pp operation, and is 0 when the oper ation is completed. the device internally resets the write enable latch to 0 before the operation co mpletes (the exact timing is not specified). the device does not execute a page pr ogram (pp) command that specifies a page that is protected by the block protect bits (see table 7.1 on page 13 ). table 11.5 protection modes wp#/acc signal srwd bit mode write protection of the status register protected area (see note) unprotected area (see note) 11 software protected (spm) status register is writable (if the wren command has set the wel bit). the values in the srwd, bp2, bp1 and bp0 (or bp3, bp2, bp1 and bp0) bits can be changed. protected against program and erase commands ready to accept page program and sector erase commands 10 00 01 hardware protected (hpm) status register is hardware write protected. the values in the srwd, bp2, bp1 and bp0 (or bp3, bp2, bp1 and bp0) bits cannot be changed. protected against program and erase commands ready to accept page program and sector erase commands
july 2, 2007 s25FL128P_00_04 s25FL128P 31 data sheet (preliminary) figure 11.14 page program (pp) command sequence 0 3 4 33 3 2 3 1 3 0 29 2 8 10 9 8 7 6 5 4 3 2 1 3 5 3 6 3 7 38 3 9 46 45 44 4 3 42 41 40 47 4 8 49 50 51 52 5 3 54 55 207 3 2072 2076 2075 2074 2079 207 8 2077 2 3 22 21 3 21 07 6 5 4 3 2 1 0 d a t a byte 1 24-bit addre ss comm a nd d a t a byte 2 d a t a byte 3 d a t a byte 256 m s b m s b m s b m s b m s b s ck s i s ck s i 7 65 4 3 2 1 0 76 54 3 21 0 7 6 5 4 3 210 c s # c s # mode 0 mode 3
32 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.9.2 parallel mode in parallel mode, the maximum sck clock frequency is 10 mhz. the device requires a single clock cycle instead of eight clock cycles to acce ss the next data byte. th e memory content input me thod is the same as serial mode. the only difference is that a byte of da ta is input per clock cycle instead of a single bit. this means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles instead of in 2,048 clock cycles. figure 11.15 parallel page program (pp) instruction sequence notes 1. 1st byte = ?02h?. 2. 2nd byte = address 1, msb first (bits 23 through 16). 3. 3rd byte = address 2, msb first (bits 15 through 8). 4. 4th byte = address 3, msb first (bits 7 through 0). 5. 5th byte = first write data byte. 6. in parallel mode, the fastest access clock frequency (fsck) is 10 mhz (sck pin clock frequency). 7. programming in parallel mode requires an ?parallel mode entry? command (55h) before the program command. once in the parallel mode, the flash memory will not exit parallel mode until an ?exit parallel mode? (45h) command is given to the flash device, or upon power down / power up sequence completion. c s # 1 3 10 11 12 1 3 14 15 2 0 in s tr u ction (02h) addre ss byte 1 addre ss byte 2 addre ss byte 3 2 3 22 21 17 high-z m s b 90h byte 1 byte 2 byte n 16 2 3 24 3 1 3 2 33 s ck s i po[7-0] 4 20 19 1 8 16 8 0 567 8 9 15 7 n hi-z
july 2, 2007 s25FL128P_00_04 s25FL128P 33 data sheet (preliminary) 11.10 sector erase (se: 20h, d8h) the sector erase (se) command sets all bits at all addre sses within a specified sector to a logic 1. a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the se command plus three address bytes on si. any address within th e sector (see table 7.1 on page 13 ) is a valid address for the se command. cs# must be driven low for the entire duration of the se sequence. the command sequence is shown in figure 11.16 and table 11.6 . the host system must drive cs# high after the device has latc hed the 8th bit of the se command, otherwise the device does not execute the co mmand. the se operation begins as s oon as cs# is driven high. the device internally controls the timing of th e operation, which requires a period of t se . the status register may be read to check the value of the write in progress (w ip) bit while the se operation is in progress. the wip bit is 1 during the se operation, and is 0 when the oper ation is completed. the device internally resets the write enable latch to 0 before the operation co mpletes (the exact timing is not specified). the device does not execute an se command that specifie s a sector that is protec ted by the block protect bits (see table 7.1 on page 13 ). figure 11.16 sector erase (se) command sequence c s # s ck s i s o/po[7-0] m s b comm a nd 24- b it addre ss 01 2 3 45 67 8 910 2 8 29 3 0 3 1 2 3 22 21 3 2 1 0 hi-z mode 0 mode 3
34 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.11 bulk erase (be: c7h, 60h) the bulk erase (be) command sets all the bits within the entire memory array to logic 1s. a wren command is required prior to writing the pp command. for 64 kb sector devices, the bulk erase command may be written as eit her c7h or 60h. for 256 kb sector devices, only the c7h command is valid. the host system must drive cs# low, and then write the be command on si . cs# must be driven low for the entire duration of the be sequence. the command sequence is shown in figure 11.17 and table 11.6 . the host system must drive cs# high after the device has latched the 8th bit of the ce command, otherwise the device does not execute the co mmand. the be operation begins as s oon as cs# is driven high. the device internally controls the timing of th e operation, which requires a period of t be . the status register may be read to check the value of the write in progress (w ip) bit while the be operation is in progress. the wip bit is 1 during the be operation, and is 0 when the oper ation is completed. the device internally resets the write enable latch to 0 before the operation co mpletes (the exact timing is not specified). the device only executes a be command if all block protect bits (bp2:bp0 or bp3:bp0) are 0 (see table 7.1 on page 13 ). otherwise, the device ignores the command. figure 11.17 bulk erase (be) command sequence 01 2 4 56 7 comm a nd c s # s ck s i 3 s o/po[7-0] hi-z mode 0 mode 3
july 2, 2007 s25FL128P_00_04 s25FL128P 35 data sheet (preliminary) 11.12 deep power down (dp: b9h) the deep power down (dp) command provides the lo west power consumption m ode of the device. it is intended for periods when the device is not in active use, and ignores all commands except for the release from deep power down (res) command. the dp mode therefore provides the maximum data protection against unintended write operations. the standard standby mode, which th e device goes into automatically when cs# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. the host system must drive cs# low, and then write th e dp command on si. cs# must be driven low for the entire duration of the dp sequence. the command sequence is shown in figure 11.18 and table 11.6 . the host system must drive cs# high after the device has latched the 8th bit of the dp command, otherwise the device does not execute the command. after a delay of t dp, the device enters the dp mode and current reduces from i sb to i dp (see table 17.1 on page 41 ). once the device has entered the dp mode, all commands are ignored except the res command (which releases the device from the dp mode). the res comm and also provides the electronic signature of the device to be output on so, if desired (see sections 11.13 and 11.14) . dp mode automatically terminates when power is remov ed, and the device always powers up in the standard standby mode. the device rejects any dp command issued while it is executing a program, erase, or write status register operation, and c ontinues the operation uninterrupted. figure 11.18 deep power down (dp) command sequence c s # s ck s i s o/po[7-0] s t a nd b y mode deep power-down mode comm a nd 0 1 2 3 4567 t dp hi-z mode 0 mode 3
36 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.13 release from deep power down (res: abh) the device requires the release from deep power down (res) command to exit the deep power down mode. when the device is in the deep power do wn mode, all commands except res are ignored. the host system must drive cs# low and write the res command to si. cs# must be driven low for the entire duration of the sequence. the command sequence is shown in figure 11.19 and table 11.6 . the host system must drive cs# high t res(max) after the 8-bit res command byte. the device transitions from dp mode to the standby mode after a delay of t res (see table 19.1 on page 42 ). in the standby mode, the device can execute any read or write command. figure 11.19 release from deep power down (res) command sequence 11.14 release from deep po wer down and read electro nic signature (res: abh) 11.14.1 serial mode this command reads the old-styl e electronic signature from th e so serial output pin. see figure 11.20 and table 11.6 for the command sequence and signature value. please note that the el ectronic signature only consists of the device id portion of the 16-bit jedec id that is read by the read id entifier (rdid) instruction. the old style electronic signature is supported for backw ard compatibility, and should not be used for new software designs, which should instead use the jedec 16-bit electronic signature by issuing the read identifier (rdid) command. the device is first selected by driving the cs# chip sele ct input pin to the logic low state. the res command is shifted in followed by three dummy bytes onto the si serial input pin. after the last bit of the three dummy bytes is shifted into the device, a byte of electronic sign ature will be shifted out of the so serial output pin. each bit is shifted out during the falling edge of the sc k serial clock signal. the maximum clock frequency for the res (abh) command is at 104 mhz. the electronic signature can be read repeatedly by applying multiples of eight clock cycles. the res instruction sequence is terminated by driving th e cs# chip select input pin to the logic high state anytime during data output. after issuing any read id commands (90h, 9fh, abh), driving the cs# chip select input pin to the logic high state will automatica lly send the device into the standby mode. driving the cs# chip select input pin to the logic low state again will automatically sent the device out of the standby mode and into the active mode. c s # s ck s i s o/po[7-0] 0 1 2 3 4 5 6 7 comm a nd deep power-down mode t re s s t a nd b y mode mode 0 hi-z mode 3
july 2, 2007 s25FL128P_00_04 s25FL128P 37 data sheet (preliminary) figure 11.20 serial release from deep power down and read electronic signature (res) command sequence 11.14.2 parallel mode when the device is in parallel mode, the maximum sc k clock frequency is 10 mhz. the device requires a single clock cycle instead of eight clock cycles to acce ss the next data byte. the method of memory content output will be the same compared to outside of parallel mo de. the only difference is that a byte of data is output per clock cycle instead of a sing le bit. in this case, the electron ic signature will be output onto the p0[7?0] serial output pins. figure 11.21 parallel release from deep power down and read electronic signature (res) command sequence notes 1. in parallel mode, the maximum access clock frequency (fsck) is 10 mhz (sck pin clock frequency). 2. to release the device from deep power down and read electronic id in parallel mode, a parallel mode enter command (55h) must be issued before the res command. the device will not exit parallel mode until a parallel mode exit command (45h) is written, or upon power-down or powe r-up sequence. 3. byte 1 will output the electronic signature. c s # s ck s i s o 3 d u mmy byte s hi-z m s b deep power-down mode s t a nd b y mode 0 1 2 3 4567 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 electronic id o u t comm a nd t re s 2 3 22 21 3 2 10 7 65 4 3 2 1 0 m s b c s # s ck s i po[7-0] 3 d u mmy byte s electronic id hi-z deep power-down mode s t a nd b y mode 0 1 2 3 4567 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 comm a nd t re s 2 3 22 21 3 2 10 m s b byte 1
38 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 11.15 command definitions note for 64 kb sector devices, either command is valid and performs the same function. 12. program acceleration via wp#/acc pin the program acceleration function requires applying v hh to the wp#/acc input, and then waiting a period of t wc . minimum t vhh rise and fall times is required for wp#/acc to change to v hh from v il or v ih . removing v hh from the wp#/acc pin returns the device to normal operation after a period of t wc . figure 12.1 acc program acceleration timing requirements note only read status register (rdsr) and page program (pp) operations are allow when acc is at (v hh ). table 11.6 command definitions operation command description one-byte command code address bytes dummy byte data bytes read read read data bytes 03h (0000 0011) 3 0 1 to fast_read read data bytes at higher speed 0bh (0000 1011) 3 1 1 to rdid read identification 9fh (1001 1111) 0 0 1 to 3 read_id read manufacturer id and device id 90h (1001 0000) 3 0 1 to write control wren write enable 06h (0000 0110) 0 0 0 wrdi write disable 04h (0000 0100) 0 0 0 erase se 64 kb sector erase (see note) 20h (0010 0000) or d8h (1101 1000) 30 0 256 kb sector erase d8h (1101 1000) 3 0 0 be bulk (chip) erase, uniform 64 kb sector product (see note) c7h (1100 0111) or 60h (0110 0000) 00 0 bulk (chip) erase, uniform 256 kb sector product c7h (1100 0111) 0 0 0 program pp page program 02h (0000 0010) 3 0 1 to 256 status register rdsr read from status register 05h (0000 0101) 0 0 1 to wrsr write to status register 01h (0000 0001) 0 0 1 parallel mode entry enter x8 parallel mode 55h (0101 0101) 0 0 0 exit exit x8 parallel mode 45h (0100 0101) 0 0 0 power saving dp deep power down b9h (1011 1001) 0 0 0 res release from deep power down abh (1010 1011) 0 0 0 release from deep power down and read electronic signature abh (1010 1011) 0 3 1 to acc t vhh v hh v il or v ih v il or v ih t vhh t wc t wc comm a nd ok comm a nd ok table 12.1 acc program acceleration specifications parameter description min. max. unit v hh acc pin voltage high 8.5 9.5 v t vhh acc voltage rise and fall time 250 ns t wc acc at v hh and v il or v ih to first command 5ns
july 2, 2007 s25FL128P_00_04 s25FL128P 39 data sheet (preliminary) 13. power-up and power-down during power-up and power-down, certain conditions mu st be observed. cs# must follow the voltage applied on v cc , and must not be driven low to select the device until v cc reaches the allowable values as follows (see figure 13.1 and table 13.1 ): ? at power-up, v cc (min.) plus a period of t pu ? at power-down, v ss a pull-up resistor on chip select (cs#) typically meets proper power-up and power-down requirements. no write status register, progr am, or erase command should be sent to the device until v cc rises to the v cc minimum, plus a delay of t pu . at power-up, the device is in standby mode (not deep power down mode) and the wel bit is reset (0). each device in the host system should have the v cc rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the or der of 0.1 f), as a precaution to stabilizing the v cc feed. when v cc drops from the operating voltage to below the minimum v cc threshold at power-down, all operations are disabled and the device does not res pond to any commands. note that data corruption may result if a power-down occurs while a write regi ster, program, or erase operation is in progress. figure 13.1 power-up timing diagram 14. initial delivery state the device is delivered with all bits set to 1 (each byte contains ffh) upon initial factory shipment. the status register contains 00h (all status register bits are 0). table 13.1 power-up timing characteristics symbol parameter min max unit v cc(min) v cc (minimum) 2.7 v t pu v cc (min) to device operation 15 ms v cc v cc (max) v cc (min) full device access t pu time
40 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 15. absolute maximum ratings do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. these are stress ratings only and device oper ation at these or any other conditions beyond those indicated in this section and in the operating ranges section of this document is not implied. device operation for extended periods at the limits listed in this section may affect device reliability. notes 1. minimum dc voltage on input or i/o pins is ?0.5 v. du ring voltage transitions, input at i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 15.2 . maximum dc voltage on output and i/o pins is 3.6 v. during voltage transitions output pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 15.2 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 15.1 maximum negative overshoot waveform figure 15.2 maximum positive overshoot waveform 16. operating ranges note operating ranges define those limits between wh ich functionality of the device is guaranteed. table 15.1 absolute maximum ratings description rating ambient storage temperature ?65c to +150c voltage with respect to ground: all inputs and i/os ?0.5 v to v cc +0.5 v 20 n s 20 n s +0. 8 v ?0.5 v 20 n s ?2 v 20 n s 20 n s v cc +2.0 v v cc +0.5 v 20 n s 2.0 v table 16.1 operating ranges description rating ambient operating temperature (t a ) industrial ?40c to +85c positive power supply voltage range 2.7 v to 3.6 v
july 2, 2007 s25FL128P_00_04 s25FL128P 41 data sheet (preliminary) 17. dc characteristics this section summarizes the dc char acteristics of the device. designers should check that the operating conditions in their circuit match the measurement c onditions specified in the test specifications in table 18.1 on page 41 , when relying on the quoted parameters. note typical values are at t a = 25 c and 3.0 v. 18. test conditions figure 18.1 ac measurements i/o waveform table 17.1 dc characteristics (cmos compatible) parameter description test conditions (see note) min typ. max unit v cc supply voltage 2.7 3.6 v i cc1 active read current sck = 0.1 v cc / 0.9v cc 104 mhz (serial) 22 ma sck = 0.1 v cc / 0.9v cc 40 mhz (serial: fast read mode) 10 ma 3 mhz (parallel mode) 10 ma i cc2 active page program current cs# = v cc 26 ma i cc3 active wrsr current cs# = v cc 26 ma i cc4 active sector erase current cs# = v cc 26 ma i cc5 active bulk erase current cs# = v cc 26 ma i sb standby current v in = gnd or v cc , cs# = v cc 200 a i dp deep power down current v in = gnd or v cc , cs# = v cc 320a i li input leakage current v in = gnd or v cc , v cc = v cc max 2 a i lo output leakage current v in = gnd to v cc , v cc = v cc max 2 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?0.1 ma v cc ? 0.6 v table 18.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0. 8 v cc 0.2 v cc 0.7 v cc 0. 3 v cc inp u t level s inp u t a nd o u tp u t 0.5 v cc
42 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 19. ac characteristics notes 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0 v; 10,000 cycles; checkerboard data pattern 2. under worst-case conditions of 90 c; v cc = 2.7v; 100,000 cycles 3. not 100% tested. 4. fast_read is not valid in parallel mode. 5. only applicable as a constraint for wrsr command when srwd is set to a ?1?. table 19.1 ac characteristics symbol parameter min typ (notes) max (notes) unit f sck sck clock frequency read command d.c. 40 (serial) 6 (parallel) mhz f sck sck clock frequency for: fast_read, rdid, read_id, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr (note 4) d.c. 104 (serial) 10 (parallel) mhz t crt clock rise time (slew rate) 0.1 (serial) 0.25 (parallel) v/ns t cft clock fall time (slew rate) 0.1 (serial) 0.25 (parallel) v/ns t wh sck high time 4.5 (serial) 50 (parallel) ns t wl sck low time 4.5 (serial) 50 (parallel) ns t cs cs# high time 100 (serial) 20 (parallel) ns t css cs# setup time (note 3) 3ns t csh cs# hold time (note 3) 3ns t hd hold# setup time (relative to sck) (note 3) 3ns t cd hold# non-active hold time (relative to sck) (note 3) 3ns t hc hold# non-active setup time (relative to sck) 3 ns t ch hold# hold time (relative to sck) 3 ns t v output valid 0 8 (serial) 20 (parallel) ns t ho output hold time 0 ns t hd:dat data in hold time 2 (serial) 10 (parallel) ns t su:dat data in setup time 3 (serial) 10 (parallel) ns t r input rise time 5ns t f input fall time 5ns t lz hold# to output low z (note 3) 8 (serial) 20 (parallel) ns t hz hold# to output high z (note 3) 8 (serial) 20 (parallel) ns t dis output disable time (note 3) 8 (serial) 20 (parallel) ns t wps write protect setup time (notes 3 , 5 )20ns t wph write protect hold time (notes 3 , 5 ) 100 ns t w write status register time 100 ms t dp cs# high to deep power down mode 3s t res release dp mode 30 s t pp page programming time 1.5 (note 1) 3 (note 2) ms t ep page programming time (wp#/acc = 9 v) 1.2 (note 1) 2.4 (note 2) sec t se sector erase time (64 kb) 0.5 (note 1) 3 (note 2) sec t se sector erase time (256 kb) 2 (note 1) 12 (note 2) sec t be bulk erase time 128 (note 1) 768 (note 2) sec
july 2, 2007 s25FL128P_00_04 s25FL128P 43 data sheet (preliminary) figure 19.1 spi mode 0 (0,0) input timing figure 19.2 spi mode 0 (0,0) output timing c s # s ck s i s o t c s h t c ss t c s h t c ss t crt t cft m s b in l s b in hi-z t s u:dat t hd:dat t c s c s # s ck s o l s b out t wh t wl t di s t v t ho t v t ho
44 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) figure 19.3 hold# timing figure 19.4 write protect setup and hold timing during wrsr when srwd=1 t ch t hz t cd t hd t hc t lz c s # s ck s o s i hold# wp#/acc c s # s ck s i s o hi-z t wp s t wph
july 2, 2007 s25FL128P_00_04 s25FL128P 45 data sheet (preliminary) 20. physical dimensions 20.1 so3 016 wide?16-pin plastic small outline package (300-mil body width) 3601 \ 16-038.03 \ 8.31.6 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane. . package so3 016 (inches) so3 016 (mm) jedec ms-013(d)aa ms-013(d)aa symbol min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 a2 0.081 0.104 2.05 2.55 b 0.012 0.020 0.31 0.51 b1 0.011 0.019 0.27 0.48 c 0.008 0.013 0.20 0.33 c1 0.008 0.012 0.20 0.30 d 0.406 bsc 10.30 bsc e 0.406 bsc 10.30 bsc e1 0.295 bsc 7.50 bsc e .050 bsc 1.27 bsc l 0.016 0.050 0.40 1.27 l1 .055 ref 1.40 ref l2 .010 bsc 0.25 bsc n 16 16 h 0.10 0.30 0.25 0.75 0? 8? 0? 8? 1 5? 15? 5? 15? 2 0? 0?
46 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) 20.2 wson 8-contact (6 x 8 mm) no-lead package 3408\ 16-038.28a notes: 1. dimensioning and tolerancing conforms to asme y14.5m-1994. 2. all dimensions are in millimeters, sym is in degrees. 3. n is the total number of terminals. 4. dimension b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. nd refers tot he number of terminals on d side. 6. maximum package warpage is 0.05 mm. 7. maximum allowable burrs is 0.076 mm in all directions. 8. pin #1 id on top will be laser marked. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10. a maximum 0.15 mm pull back (l1) may be present. quad flat no lead packages (wsnb) - plastic dimensions symbol min nom max note e 1.27 bsc n83 nd 4 5 l 0.45 0.50 0.55 b 0.35 0.40 0.45 4 d2 4.70 4.80 4.90 e2 6.30 6.40 6.50 d 6.00 bsc e 8.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 l1 0.15 max. 10 0 --- 12 2 k 0.20 min. side view a1 a 9. seating plane c 0.05 c 0.10 c top view b e a d n 8. 0.30 dia typ. 2 1 2x c 0.10 2x c 0.10 bottom view nx l d2/2 2 1 d2 9. (datum a) pin #1 id r0.20 e2/2 e2 k 4. nx b n-1 e n 5. (nd-1) x e see detail "a" c m . 0.05 b a c m . 0.10 detail "a" datum a 4. 10. l1 terminal tip e e/2 l
july 2, 2007 s25FL128P_00_04 s25FL128P 47 data sheet (preliminary) 21. revision history section description revision 01 (january 12, 2007) initial release. revision 02 (march 13, 2007) distinctive characteristics changed standby mode current. s25FL128P sector address table (uniform 64 kb sector) corrected addresses for sectors 0 and 32. parallel mode (for 16-pin so package only) added last sentence in section. read status register (rdsr: 05h) separated status r egister bit descriptions in to an additional subsection. page program (pp: 02h) modified parallel page program (pp) instruction s equence figure to match format of other parallel mode figures. command definitions changed code for bulk erase (be) 256 kb product in table. read manufacturer and device id (read_id: 90h) corrected si and clk in parallel read_id instruction sequence figure. absolute maximum ratings added overshoot and undershoot information. dc characteristics changed maxi mum specifications for i cc1 (parallel mode), i sb , and i dp . revision 03 (april 24, 2007) ordering information changed valid combinations table. revision 04 (july 2, 2007) device operations added a sentence to byte or page programming parallel mode (for 16-pin so package only) added a sentence.
48 s25FL128P s25FL128P_00_04 july 2, 2007 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries. other names used are for informational purp oses only and may be trademarks of their respective owners.

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